1. Field of the Invention
The present invention relates to a semiconductor memory device in which the memory cell of a CMOS static RAM is formed.
2. Description of the Prior Art
FIG. 4 is a top surface view of the main part showing a conventional semiconductor memory device. Referring to the figure, P-type-impurities-implanted diffused area 1 is formed in the upper part of a strip-shaped N well, N-type-impurities-implanted diffused area 2 is formed in the upper part of a strip-shaped P well adjacent to the N well, N-type-impurities-implanted N well contact area 3 is formed in the upper part of the N well, and P-type-impurities-implanted P well contact area 4 is formed in the upper part of the P well.
The operation will next be described.
A semiconductor memory device has a plurality of memory cells formed in a matrix state therein. When a memory cell of one bit is a Full-CMOS type SRAM memory cell consisting of six transistors for instance, the memory cell is formed extending across at least one N well and one P well.
An example in which a N well and a P well are alternately formed in rows is shown in FIG. 4. Each of wells constitutes a gate electrode on an active-layer area to be implanted by impurities, to thereby form a transistor. The active-layer area implanted by impurities corresponds to the source terminal and the drain terminal of the transistor.
Impurities of a conduction type opposing the conduction type of the well are implanted into the areas where the source terminal and the drain terminal of the transistor are formed. For instance, a PMOS transistor is formed by means of implanting P type impurities into a N well (A PMOS transistor is formed within diffused area 1). On the other hand, a NMOS transistor is formed by means of implanting N type impurities into a P well (A NMOS transistor is formed within diffused area 2). Incidentally, because the active layer of the area into which impurities of the same conduction type as the type of the well were implanted is in a state electrically connected with the well, the active layer forms a well contact area (N well contact area 3 and P well contact area 4) for fixing the electric potential of the well.
A well contact area is provided for a plurality of memory cell rows in order to give a predetermined fixed potential to each of the wells.
That is, in order to reduce the size of the cell, the well contact for giving the well potential is not provided within the memory cell of one bit. However, in order to uniformly give the potential to each of the wells, it is necessary to arrange the well contacts at intervals of the extent to which the voltage drop caused by the resistance component of the well can be sufficiently neglected. For instance, a well contact area is provided on every 32 rows or 64 rows of memory cells.
Because the conventional semiconductor memory device has been arranged as mentioned above, N well contact area 3 formed in the upper part of the N well has the conduction type opposing the conduction type of diffused area 1 constituting the row of memory cells because impurities of the same conduction type as the conduction type of the N well are implanted thereinto. In a similar manner, P well contact area 4 formed in the upper part of the P well has the conduction type opposing the conduction type of diffused area 2 constituting the row of memory cells because impurities of the same conduction type as the conduction type of the P well are implanted thereinto. For this reason, because N well contact area 3 and P well contact area 4 become isolated-small-island shaped, a highly developed microfabrication technology for forming these areas is required. As a result, there has been a drawback that these areas are occasionally not successfully formed.
For instance, in the process in which N well contact area 3 and P well contact area 4 are manufactured, the disappearance or fall of a resist remaining in an island shape is caused in the photolithographical process, and thereby the implantation of impurities is occasionally not successfully performed.
The present invention has been accomplished to solve the above-mentioned problem, and an object of the present invention is to provide a semiconductor memory device in which the occurrence of the disappearance or fall of the resist is suppressed, to thereby reduce the occurrence of defectives in the manufacturing process.
According to a first aspect of the present invention, there is provided a semiconductor memory device in which a N well contact area is integrally formed with a second diffused area in the upper parts of a N well and a P well, and a P well contact area is integrally formed with a first diffused area in the upper parts of the P well and the N well.
Here, the N well contact area and the P well contact area may be alternately formed in the direction of a row.
In addition, a power line for supplying electric power to the N well may be wired within the N well contact area, and a grounding conductor for grounding the P well may be wired within the P well contact area.
At least one row of memory cells can be formed between the N well contact area and the P well contact area.
A signal line for timing adjustment can be wired within the N well contact area.
Alternatively, a signal line for timing adjustment can be wired within the P well contact area.